1. Field of the Invention
The present invention relates to a process for manufacturing MOS-type integrated circuits.
2. Discussion of the Related Art
The need for forming large numbers of electrically connected devices on the same substrate requires that the devices be located physically as close together as possible, while at the same time operating independently in the same way as discrete components.
For this purpose, special prior art insulating techniques have been devised for minimizing the space required for ensuring correct insulation of adjacent devices, enabling a high degree of integration. Reducing the size of each device, in fact, provides for reducing the total area of the integrated circuit, thus enabling a larger number of circuits to be formed on the same wafer, and a substantial reduction in circuit cost.
One such prior art technique widely used for NMOS, PMOS and CMOS circuits is the LOCOS (LOCal Oxidation of Silicon) technique, which includes defining the active areas by depositing a layer of nitride, implanting channel stoppers in predetermined regions of the substrate through a mask, and growing field oxide regions in the portions which are not covered by the nitride layer. The advantages of the LOCOS technique are the following: simplicity; the possibility of implanting channel stoppers automatically aligned with the active regions (as required for micrometric and submicrometric technology); and precise definition of the active areas.
An example of the prior art LOCOS insulating technique will be described with reference to FIGS. 1-4, which show the formation of an N and P type transistor and EPROM memory cell of an N-well CMOS device.
FIG. 1 shows an intermediate structure produced by forming an N-well 2 in a P type substrate 1; growing an oxide layer 3 ("pad oxide") on the substrate 1; depositing a layer of nitride 4 on pad oxide 3; and simultaneously defining N and P type active areas by masking and subsequently etching the nitride layer 4. The FIG. 1 structure, therefore, comprises a substrate 1 housing an N-well 2 and selectively covered (in the portions defining the active areas of the finished integrated circuit) with an oxide layer 3, a nitride layer 4, and a photoresist masking layer 5.
At this point, a second masking operation, shown in FIG. 2, is performed for protecting the N type regions prior to implanting the channel stoppers, and which operation includes covering the N-well region with a resist mask 6 (FIG. 2), followed by performing a high-energy boron implantation as shown by arrows 7.
Implantation and diffusion of boron ions: inside the substrate 1 results in the formation of P+ type channel stoppers 8 inside the unmasked portions of the substrate, at which point, resist layers 5 and 6 are removed, and, via field oxidation, field oxide regions 10 are formed, with intrusion of the oxide beneath the nitride layer 4 along the edge of the active areas (thus forming the so-called "field beak"), as shown in FIG. 3.
In the example described and shown, the process continues, as shown in FIG. 4, by removing nitride layer 4; growing a gate oxide layer 13; depositing and doping (via phosphorus or POCl.sub.3 implantation) a first polysilicon layer 14; defining the first polysilicon layer 14 in the memory matrix region and the parts of the circuit featuring UPROM (Unerasable Programmable Read Only Memory) cells which require the first polysilicon layer 14 for forming floating gates; growing and removing an intermediate oxide layer 15 in the cell-free circuit regions; and depositing a second polysilicon layer 16 using the known Double Short Circuited Polysilicon technique whereby the second polysilicon layer 16 contacts the first polysilicon layer 14 in the cell-free circuit regions, and is separated from the first polysilicon layer 14 in the cell regions by the intermediate oxide layer 15.
The above phases result in the formation of the intermediate structure shown in FIG. 4, which structure includes presents substrate 1; well 2; field oxide regions 10; channel stoppers 8; gate oxide layer 13; first polysilicon layer 14; intermediate oxide layer 15; and second polysilicon layer 16. For the sake of simplicity, layers 14 and 16 in FIG. 4 are also illustrated separately in the circuit region (to the left of the structure) the two layers would merge to form the transistor gates.
In the prior art LOCOS technique described and shown, high-energy implantation (as shown by arrows 7 in FIG. 2) provides for raising the turn-on threshold voltage of the parasitic transistors formed by the interconnecting lines over the field oxide regions, and which, in the event of an overly thin field oxide region or insufficient doping of the substrate, may result in inversion of the conductivity of the silicon region underlying the field oxide region, thus reducing or even jeopardizing the electric performance of the finished integrated circuit. As the threshold voltage of the parasitic transistors, however, increases in proportion to doping ion concentration, the above phenomenon is prevented by increasing the doping concentration at the silicon-field-oxide interface, so that the threshold voltage of the parasitic transistors is greater than the maximum operating voltage of the integrated circuit. For this purpose, ions of the same type as the substrate (in this case, boron) are high-energy implanted for ensuring correct isolation and preventing segregation of the doping agent in the oxide during field oxidation.
Whereas the threshold voltage of the parasitic transistors increases, the breakdown voltage of the junction formed between the channel stopper and the active areas decreases alongside an increase in doping ion concentration. Moreover, the presence of the junction also creates a parasitic capacitance, due to the depletion region, which is directly proportional to channel stopper concentration close to the active areas. Such conflicting requirements, therefore, involve a tradeoff, which generally results in selecting the implant dose of the channel stopper so that the threshold voltage of the parasitic transistor and the breakdown voltage of the junction exceed the maximum voltage of any one part of the device.
As already stated, in the prior art LOCOS technique, formation of the channel stoppers beneath the field oxide regions requires an additional masking stage for preventing the N-well regions from also being doped.
Though widely used, the LOCOS technique can be improved with respect to the number of masking stages involved, which substantially affect both manufacturing and finished circuit cost, as well as with respect to the electric characteristics of the device in terms of the threshold voltage of the parasitic transistor.
Accordingly, it is an object of the present invention to provide an improved manufacturing process which reduces the number of masking stages involved in forming the channel stoppers, without jeopardizing, and while at the same time improving, the electric characteristics of the finished device.